Conguration Caching and Swapping
نویسندگان
چکیده
Speedups of coupled processor-FPGA systems over traditional microprocessor systems are limited by the cost of hardware reconguration. In this paper we compare several new con guration caching algorithms that reduce the latency of recon guration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the con gurations is reduced, lowering the con gurable overhead.
منابع مشابه
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